This invention relates to a logic synthesis method for generating a semiconductor integrated circuit from data of register transfer level. This invention particularly pertains to a logic synthesis method for generating a low-power semiconductor integrated circuit and to a low-power semiconductor integrated circuit.
In recent years, a procedure known as a top-down design method has been used to lay out semiconductor integrated circuits. In the top-down design method, a targeted semiconductor integrated circuit is represented using functional descriptions of register transfer level (RTL). The processing of logic synthesis with the aid of RTL functional descriptions is carried out to generate targeted semiconductor integrated circuits.
FIG. 24 shows a usual RTL functional description. FIG. 25 shows a logic circuit, i.e., a semiconductor integrated circuit, which is generated by means of a logic synthesis technique using the FIG. 24 RTL functional description.
The FIG. 24 RTL functional description is one which specifies, at functional level, data transfer between registers. r1, r2, r3, and r4 represent respective registers, func1, func2, func3, and func4 are functional descriptions of combinational logic circuits connected between the registers. xe2x80x9cassignxe2x80x9d and xe2x80x9calwaysxe2x80x9d are sentences describing the connections of the registers with the combinational logic circuits.
When synthesizing a logic with the use of the FIG. 24 RTL functional description, it is determined on an area/rate tradeoff curve by giving area or rate constraint requirements.
In a logic of FIG. 25 generated from the FIG. 24 RTL functional description, 101, 103, 105, and 107 are flip-flops as a result of the mapping of the registers r1, r2, r3, and r4 by means of logic synthesis. The flip-flops 101, 103, 105, and 107 directly correspond to the respective registers r1, r2, r3, and r4. 108 is a clock buffer. 100, 102, 104, and 106 are combinational logic circuits respectively corresponding to func1, func2, func3, and func4 of FIG. 24 RTL functional description. The combinational logic circuits 100, 102, 104, and 106 are circuits that are mapped from the FIG. 24 RTL functional description as a single circuit on an area/rate tradeoff curve.
The power consumption P of the semiconductor integrated circuit can be found by:
P=fxc3x97Cxc3x97V2 
where f is the operating frequency, C the load capacitance, and V the supply voltage. There are three ways of reducing the power consumption of the semiconductor integrated circuit. The first way is to reduce the operating frequency f. The second way is to reduce the load capacitance C. The third way is to reduce the supply voltage V. Of these three ways the third one is considered as the most effective way.
The third way, however, produces the problem that if the supply voltage is set low, this increases the delay time of a critical path that has the maximum delay time among a great many paths together forming a logic circuit.
With a view to providing a solution to the above-described problem, Japanese Patent Application, published under Pub. No. 5-299624, shows a technique. In accordance with this technique,  discloses that logic gates, not required to operate at a high speed, are driven by a low-voltage source, whereas other logic gates, required to operate at a high speed, are driven by a high-voltage source. In other words, this technique is trying to reduce the overall power consumption of the semiconductor integrated circuit by driving only logic gates constituting a critical path using high voltage, without increasing the delay time of critical path. This technique, however, suffers the following drawbacks.  However, the foregoing Japanese Patent Application fails to disclose the use of two voltage sources comprising a high and low voltage source in conjunction with any given critical path.
When downloading data from a low-voltage driven, slow-speed logic gate to a high-voltage-driven, high-speed logic gate, this requires the provision of a level converter between these two logic gates in order that the output of the former logic gate increases in voltage level. Such is shown in Japanese Patent Application, published under Pub. No. 5-67963. Each combinational logic circuit of FIG. 25 is made up of a great many logic gates (see FIGS. 26 and 27). Suppose a critical path is one represented by bold line in the figures. In order to drive such a critical path by a high-voltage source, a level converter must be arranged at points marked with symbol ∘. In FIG. 26, eight level converters muse be placed. In FIG. 27, 12 level converters must be placed. Semiconductor integrated circuits of large-scale integration contain a great number of combinational logic circuits, therefore containing a great number of logic gates. Accordingly, in a semiconductor integrated circuit of large-scale integration, a great number of level converters must be arranged in a single combinational logic circuit with a critical path. Further, there are many combinational logic circuits containing a critical path. This means that the entire semiconductor integrated circuit will have to contain an enormous number of level converters. With respect to a limited number of combinational logic circuits, it is possible to locate where to arrange level converters. However, if the entire semiconductor integrated circuit of large-scale integration is concerned, to locate where to arrange level converters is considerably troublesome and is a time consuming job. Complicated design work is required.
Bearing in mind the above-mentioned problems with the prior art techniques, the present invention was made. It is therefore an object of the present invention to provide an improved logic synthesis method  design method for designing a semiconductor device which is  capable of facilitating the generation of low-power semiconductor integrated circuits without increasing the delay time of a critical path contained in each combinational logic circuit of a targeted semiconductor integrated circuit. It is another object of the present invention to provide a low-power semiconductor integrated circuit, without causing the delay time of the circuit path to increase.
In other words, an object of the present invention is to reduce the overall power consumption of the semiconductor integrated circuit by driving only logic gates constituting a critical path using high voltage, without increasing the de time of the critical path.
The following points were considered so as to accomplish the above-described objects of the present invention. As shown in FIG. 25, a semiconductor integrated circuit comprises a great many registers and a great many combinational logic circuits arranged between the registers. If a level converter is arranged within the register, this eliminates the need for providing a level converter at every point requiring the provision of a level converter when driving a critical path by a high-voltage source. This cuts down the number of points where a level converter must be placed. If a register is provided with a level converter, then it becomes necessary to drive an entire combinational logic circuit to which the level converter applies data by a high-voltage source. However, the number of logic gates along a critical path is about 5% of the total number of logic gates in the entire semiconductor integrated circuit. Therefore, the ratio of the number of combinational logic circuits with a critical path versus the total number of combinational logic circuits contained in the entire semiconductor integrated circuit is negligible. Because of this, driving a combinational logic circuit with a critical path by a high-voltage source will not greatly increase the power consumption of the semiconductor integrated circuit.
The present invention provides a logic synthesis method for synthesizing, based on connection information of logic cells, a semiconductor integrated circuit of a plurality of registers and a plurality of combinational logic circuits connected between the registers. This logic synthesis method comprises:
a first step for mapping, when there exists among the plural combinational logic circuits a combinational logic circuit with a signal propagation delay time below a design delay upper limit, such a combinational logic circuit into a combinational logic circuit of a first type driven by a low-voltage source, and for mapping, when there exists among the plural combinational logic circuits a combinational logic circuit with a signal propagation delay time above the design delay upper limit, such a combinational logic circuit into a combinational logic circuit of a second type driven by a high-voltage source;
a second step for determining which of the combinational logic circuits of the first type outputs to a combinational logic circuit of the second type and for remapping a combinational logic circuit of the first type, determined to output to a combinational logic circuit of the second type, into the second-type: and
a third step for determining which of the registers generates a signal to a combinational logic circuit of the second type, for mapping a register, determined to generate a signal to a combinational logic circuit of the second type, into a register driven by the high-voltage source, and for mapping a register, determined not to generate a signal to a combinational logic circuit of the second type, into a register driven by the low-voltage source.
The present invention provides a semiconductor integrated circuit having a plurality of registers and a plurality of combinational logic circuits connected between the registers. In this semiconductor integrated circuit:
part of the plural combinational logic circuits are formed by respective combinational logic circuit of a first type driven by a low voltage source and the remaining part of the plural combinational logic circuits are formed by respective combinational logic circuits of a second type driven by a high-voltage source; and
of the plural registers a register that has a combinational logic circuit of the first type on its input side and a combinational logic circuit of the second type on its output side is a circuit that has a temporary data storage driven by the low-voltage source and a level converter which is driven by the high-voltage source and which converts a low-voltage-level output signal, received from the temporary data storage, into a high-voltage-level output.
The action of the present invention is as follows. A semiconductor integrated circuit is made up of many registers and many combinational logic circuits connected between the registers, and some of these combinational logic circuits have a critical path. A register arranged upstream of a combinational logic circuit with a critical path, i.e., a register that applies data to such a critical-path-contained combinational logic circuit, is provided with a level converted. The critical-path-contained combinational logic circuits are driven by a high-voltage source. The remaining other combinational logic circuits are driven by a low-voltage source.
Since every combinational logic circuit with a critical path is driven by the high-voltage source, the delay time of the critical path is held to below a design delay upper limit. Because of the provision of a level converter as described above, the number of level converters required can be reduced in comparison with a ease in which only critical paths are driven by the high-voltage source. This considerably facilitates the semiconductor integrated circuit design. Even when driving each combinational logic circuit with a critical path by a high-voltage source, the increase in power consumption is held low since the ratio of the number of combinational logic circuits with a critical path to the total number of combinational logic circuits with a critical path to the total number of combinational logic circuits is negligible. Meanwhile, the other combinational logic circuits without a critical path are driven by the low-voltage source, this greatly contributes to the reduction of the power consumption of the semiconductor integrated circuit.